1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to a logic integrated circuit constructed by using Schottky junction type field effect transistors that employ GaAs.
2. Description of the Prior Art
In an integrated circuit having a plurality of GaAs field effect transistors (referred to as FETs hereinafter), there appears a nonuniformity in the values of the threshold voltage which is caused by the differences in individual fabrication processes. In other words, the threshold voltage varies from one FET to another. For this reason, all the FETs used in the prior art integrated circuits are of the depletion-mode FETs.
There are cases in which logic circuits are constructed using integrated circuits having the depletion-mode FETs. Such a logic circuit has a buffered FET logic (referred to as BFL circuit hereinafter) for output.
A logic circuit of this kind is connected to a power supply for the drain which supplies the ground potential (0 V), a first power supply for the source which supplies a voltage (-2.0 V, for example) lower than the drain power supply, and a second power supply for the source which supplies a voltage that is still lower than the first source power supply.
Now, such a logic circuit is sometimes cascade-connected to a different type of integrated circuit made of a different semiconductor material in order to construct a larger logic circuit. In a case of this kind, the logic levels of the output signals of the respective integrated circuits have to be matched with high accuracy. Since the logic level is directly related to the voltage of the first source power supply, the allowable specification of variations in the voltage of the first source power supply has to be managed particularly rigorously. However, the power unit itself becomes costly in order to restrain the variations of the supply voltage to a strict specification value.